Rail-to-rail DAC drive circuit

ABSTRACT

A voltage mode digital-to-analog converter (DAC) with an output buffer operational amplifier is provided with a rail-to-rail output voltage capability by reducing the DAC&#39;s output voltage swing to a range that is within the amplifier&#39;s permissible input signal range, and connecting the amplifier in a multiplier configuration to produce a corresponding multiplication of its input signal. The DAC output reduction is preferably achieved by delivering an n-bit input digital signal to an n+m bit DAC, and holding the DAC&#39;s m most significant bits OFF. The m most significant bits are dummy bits that are impedance matched with the DAC, while the amplifier is an operational amplifier with a feedback circuit that is also impedance matched to the DAC.

RELATED APPLICATION

This application is a continuation-in-part of Ser. No. 08/210,618, filedMar. 18, 1994 abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital-to-analog converter (DAC) drivecircuits, and particularly to DAC circuits that are connected to outputoperational amplifiers having a permissible input voltage range lessthan the circuit's rail-to-rail differential.

2. Description of the Related Art

DACs that are configured to operate in the voltage mode, in which anoutput analog voltage that corresponds to an input digital signal isproduced, typically have their outputs buffered by an operational driveamplifier. This type of design is used, for example, in the PM-72248-bit CMOS DAC described in the Analog Devices, Inc. Data ConverterReference Manual, volume 1, 1992, pages 2-267 through 2-278.

The basic circuit is illustrated in FIG. 1. A voltage mode converterDAC1 is shown with its output 2 connected to the non-inverting input ofa buffer operational amplifier A1. The output 4 of A1 is tied back tothe amplifier's inverting input, thus providing a unity gain drive for aload 6.

A typical circuit used to implement amplifier A1 is shown in FIG. 2. Thecircuit is supplied by positive and negative voltage supply lines V_(dd)and V_(ss), respectively. The voltage supply levels are referred to asthe circuit “rails”. With V_(ss) tied to analog ground potential, thecircuit can be operated with a single power supply V_(dd), typically12-15 volts. The circuit could alternately be operated from dual powersupplies, such as +5 and −5 volts for V_(dd) and V_(ss), respectively.

The amplifier's output stage is shown as an NPN bipolar transistor Q1that provides a low-impedance, high-output current capability. Theemitter of Q1 is loaded with a current source I1, such as a 400 microampNMOS current source referenced to V_(ss), while its collector isconnected to V_(dd). Sinking the I1 current into V_(ss) allows theamplifier's output to go directly to ground.

An input stage consisting of art an NMOS transistor Q2 has its drainconnected to V_(dd), with another current source I2 sinking current fromthe source of Q2 to V_(ss); the Q2 source is also connected through aresistor R1 to the base of Q1. Transistor Q2 operates as a sourcefollower, driving the resistor R1 and output transistor Q1.

The converter DAC1 by itself is a high impedance device; the operationalamplifier A1 provides a buffer function to drive the load. However,proper operation of A1 generally requires that its input 8 from the DACbe 1 volt or more below the positive voltage supply level V_(dd). Thismeans that the voltage swing at the output of the DAC must be limited tothe permissible input voltage range for the amplifier, and consequentlyalso limits the output range for the overall circuit to a similar level.The circuit is thus limited to an output range less than a desired“rail-to-rail” voltage swing.

SUMMARY OF THE INVENTION

The present invention seeks to provide an improved DAC drive circuitthat is capable of operating in a voltage mode with a full rail-to-railoutput range. This goal is accomplished by dividing the DAC output by afactor that places it within the permissible input range for the op amp,and providing the amplifier's output stage with a gain that allows theoverall drive circuit to produce a rail-to-rail output if desired.

In a preferred embodiment the divider is implemented with an attenuationnetwork, in the form of m dummy DAC bits, that is impedance matched tothe DAC. The DAC, which is connected to receive an n-bit digital signal,thus has n+m bits. The dummy bits are connected as the DAC's m mostsignificant bits, and are always OFF. This produces a downscaling of theinput signal range by a factor ½^(m). The op amp is configured toproduce a compensating 2^(m) amplification, and includes a feedbackcircuit that is also impedance matched to the DAC. By setting m equal to1, the DAC's output range is divided by 2, with the op amp doubling theDAC's output to restore a rail-to-rail output swing.

These and other features and advantages of the invention will beapparent to those skilled in the art from the following detaileddescription, taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a known voltage mode DAC drive circuit,described above;

FIG. 2 is a schematic diagram of a known operational amplifier,described above, used in the circuit of FIG. 1;

FIG. 3 is a block diagram illustrating the basic theory of theinvention;

FIG. 4 is a block diagram showing an implementation of the inventionwith an n+m bit DAC that receives an n-bit digital input, and has its mmost significant bits held OFF to serve a dummy function; and

FIG. 5 is a simplified schematic diagram that provides additionalcircuit details of the FIG. 4 embodiment.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 presents a block diagram illustrating the inventive concept thatenables a rail-to-rail output from a voltage mode DAC that drives anoutput buffer amplifier. The output of the DAC 2 is divided by a factorD in a divide block 10 before being applied to a buffer op amp A2, whichis connected in a multiply configuration to amplify its input by afactor greater than unity. This allows the reference input for DAC 2 tobe rail-to-rail, while the swing of the input to the op amp A2 isrestricted to the rail-to-rail swing divided by D. With D set at aconvenient value such as 2, the input to the op amp A2 will only swingfrom one rail half way to the other rail. The op amp's input stage caneasily handle this voltage swing; providing it with an amplificationfactor of D results in the output from A2 as well as the input to DAC 2being rail- to- rail. This amplification is achieved in the conventionalmanner by connecting a feedback resistor RF between the output andinverting input of A2, connecting a gain setting resistor R_(F)/(D−1)between the A2 inverting input and ground, and connecting thenon-inverting input of A2 to the DAC output.

The division function is preferably implementing implemented by addingone or more dummy bits to the DAC as its most significant bits, andholding the dummy bits off continuously. While a single extra bit willdivide the DAC's output by 2, which will normally be compatible with theop amp's input stage, the concept can be generalized as illustrated inFIG. 4 by applying an n-bit digital input 12 to DAC 2, which isimplemented as an (n+m)-bit device. The division function 10 isaccomplished by holding the m most significant bits OFF. This results inan input to the op amp A2 that has a voltage range equal to therail-to-rail differential divided by 2^(m). A rail-to-rail output fromA2 is achieved by setting the amplifier's gain setting resistor equal toR_(F)/(2^(m)−1).

FIG. 5 is a simplified schematic diagram of a voltage mode DAC and theop amp A2 connected together as indicated in FIG. 4, with m=1. Theillustrated DAC employs a conventional R-2R resistance ladder, but theinvention is also applicable to other DAC voltage mode configurations.

The output from the resistor ladder is taken at node 14, which alsoprovides the input to the output amplifier A2. Voltage references REF Aand REF B are provided for the DAC at terminals 16 and 18, respectively.REF A is preferably set equal to the V_(DD) upper rail value, while REFB is preferably set equal to ground or to the lower rail value if it isdifferent from ground.

The DAC's three most significant bits (MSBs) are shown within dashedoutlines 20, 22 and 24, while the least significant bit (LSB) isenclosed within dashed outline 26. The MSB 20 is actually an attenuationnetwork that is impedance matched to the DAC and is used to divide theoutput from the DAC by two. This is accomplished by using the same R-2Rconfiguration for bit 20 as for the other bits, but holding bit 20constantly OFF regardless of the DAC's digital input signal.

A conventional decoder 28 receives the digital input signal eitherserially over a single input line 12 or as a parallel input over anumber of input lines. The decoder provides switch control signals overdecoder output lines 30 ₁, 30 ₂ . . . 30 _(n) to the various ladderstages except for the MSB 20. In this bit, the 2R resistor 32 ₀, isconnected permanently to REF B. This holds the MSB in a continual OFFstate to implement the divide-by-two function discussed above inconnection with FIG. 4. With a permanent connection to analog ground,the MSB 20 divides the DAC output by 2.

The subsequent DAC bit stages 22, 24 . . . 26 are each implemented in aconventional manner, with R-value resistors 34 ₁, 34 ₂ . . . 34 _(n)connected in series with the DAC output 14 (34 _(n) actually has a valueof 2R to terminate the ladder), and 2R value resistors 32 ₁, 32 ₂ . . .32 _(n) connected between respective pairs of R-value resistors andrespective switching networks. The 2R resistors are connected to eitherREF A or REF B, depending upon the switch control signals from thedecoder 28.

Referring first to the second MSB stage 22, the decoder output on line30 ₁ is transmitted through a pair of series connected inverters INV₁₋₁and INV₁₋₂. The 2R resistor 32 ₁ for the stage is connected to REF Athrough a first switch S_(1A) and to REF B through a second switchS_(1B). Each switch is preferably implemented with an NMOS and PMOStransistor pair connected in parallel; the gates of the PMOS transistorfor S_(1A) and NMOS transistor for S_(1B) are connected to the output ofinverter INV_(1-i), while the gates of the other transistors in S_(1A)and S_(1B) are connected in common to the output of INV₁₋₂. In this wayone of the switches S_(1A) and S_(1B) is open and the other is closed,depending upon the signal on decoder output line 30 ₁. With switchS_(1A) ON and S_(1B) OFF, the 2R resistor 32 ₁ is connected to REF A,and the bit contributes a voltage value of REF A/4 to the DAC output atterminal 14. If, on the other hand, the decoder signal causes switch S₁₈to close and switch S_(1A) to open, the 2R resistor 32 ₁ is connected toREF B. This results in a zero voltage contribution to the DAC outputwhen REF B is at ground, and a negative contribution when REF B has anegative value.

The remaining bit stages are implemented in a manner similar to thesecond MSB stage 22. Stage 24 is shown with its decoder control line 30₂ connected through series inverters INV₂₋₁ and INV₂₋₂, with its 2Rresistor 32 ₂ connected to REF A and REF B through switches S_(2A) andS_(2B), respectively. Similarly, the LSB 26 has series invertersINV_(n-1) and INV_(n-2) connected to the decoder control line 30 _(n),with its 2R resistor 32 _(n) connectable to REF A and REF B,respectively through switches S_(nA) and S_(nB). Bit 24 contributes avoltage of REF A/8 to the DAC output when switch S_(2A) is ON, while bit26 contributes a voltage of REF A/2^(n+1) when switch S_(nA) is ON.

The dummy MSB 20 includes a single switch S₀, implemented in the samemanner as the other bit switches, between its 2R resistor 320 32 ₀ andREF B. A pair of series connected inverters INV₀₋₁ and INV₀₋₂ areconnected at their input end to REF B (as opposed to the inverter pairfor the other bits, which receive respective inputs from decoder 28),and have their outputs connected to switch S₀ so as to hold the switchpermanently ON. This connects the bit's 2R resistor 32 ₀ to REF B, whichis typically grounded, and thus holds the bit 20 continually OFF. Sinceonly one of the switches in the switch pairs for each of the other bitswill be on at any given time, the dummy bit 20 is impedance matched interms of both its R-2R resistors and its switch resistance to the restof the DAC.

If the 2R resistor of each bit stage (including the MSB 20) wereconnected to REF A, the DAC output at terminal 14 would be${REF}\quad A\frac{{2N} - 1}{2N}$

(the ladder termination resistor reduces the output by the value of theLSB). When any of the branch 2R resistors are connected to ground, thenet output voltage is decremented in accordance with the bit order ofthe grounded resistors. For example, connecting the MSB 2R resistor 32032 ₀ to ground reduces the DAC output by ½, connecting the next MSB 2Rresistor 32 ₁ to ground reduces the output by ¼, and so forth. With theMSB 2R resistor 32 ₀ permanently connected to REF B as shown in FIG. 5,the DAC output can never exceed REF A/2. This is compatible with theinput voltage restrictions for the op amp A2, which as described aboveis connected in a multiplier configuration to provide a full outputswing capability from REF B up to REF A.

It is desirable that the input impedance of the feedback network for opamp A2, as seen from the op amp's inverting terminal, equal the DACoutput impedance; this will provide input bias current cancellation forthe op amp. To achieve this impedance matching, the op amp's feedbackand gain control resistors 36 and 38 each have a resistance value R,equal to the resistance values of the series resistors in the DAC.Another resistor 40 with a value of R/2 is connected between the opamp's inverting input and the junction of resistors 36 and 38. The inputimpedance for this resistor network is the resistance of resistor 40 inseries with the parallel combination of resistors 36 and 38, for a netinput impedance of R; this is the same as the DAC's R-2R outputimpedance seen from output node 14. To complete the impedance matching,a switch 42 is connected in series with resistor 40. Switch 42 isimplemented in the same manner as each of the DAC switches and is heldalways ON in a manner similar to switch SO in the dummy bit 20. Theresistance of switch 42 thus matches the net switch resistance that isincluded in the DAC's output impedance. Resistor 38 and switch 42 do notalter the op amp's gain.

While particular embodiments of the invention have been shown anddescribed, numerous variations and alternate embodiments will occur tothose skilled in the art. Accordingly, it is intended that the inventionbe limited only in terms of the appended claims.

I claim:
 1. A digital-to-analog converter (DAC) drive circuit,comprising: a pair of voltage reference nodes for supplying differentreference voltage levels, a DAC that is connected to receive an inputdigital signal, and to be supplied directly by both of said voltagereference nodes at the full reference voltage levels, said DAC havingmultiple bit positions and including m dummy bits in the mostsignificant of said bit positions, said DAC being connected to receivean n-bit input digital signal and, including said dummy bits, having n+mbits, said dummy bits being continually held OFF, and an amplifier thatis connected to receive an analog input from said DAC and to provide adrive output, said amplifier having a permissible input signal rangethat is less than the full range between said reference voltage levels,said dummy bits reducing the DAC's analog output swing to a range thatis within the amplifier's permissible input signal range, said amplifierproviding its output with a greater than unity amplification.
 2. The DACdrive circuit of claim 1, wherein said amplifier amplifies its input sothat its output has a range that extends over substantially the fullrange between said reference voltage levels.
 3. The DAC drive circuit ofclaim 2, wherein said amplifier amplifies its input signal by a factorthat is the inverse of the DAC output swing reduction provided by saiddummy bits.
 4. The DAC drive circuit of claim 1, wherein m=1.
 5. The DACdrive circuit of claim 1, said DAC comprising an R-2R ladder and anassociated switching network for connecting each of its n leastsignificant bits (LSBs) respectively to one or the other of said voltagereference nodes, said switching network including respective pairs ofswitches connected in circuit with an 2R resistor of each of said nLSBs, with one switch of each pair connecting its respective 2R resistorto one of said voltage reference nodes and the other switch of each pairconnecting its respective 2R resistor to the other of said voltagereference nodes, and a control network that turns one switch of eachpair ON and the other switch of each pair OFF in accordance with saidinput digital signal, said dummy bits each including a single switchconnecting an associated 2R dummy bit resistor to one of said voltagereference nodes that corresponds to an OFF bit output, with said singleswitch held ON for all digital inputs.
 6. The DAC drive circuit of claim5, said amplifier comprising an operational amplifier having itsnon-inverting input connected to receive the DAC output and itsinverting input connected in a feedback circuit with its output, saidfeedback circuit having an input impedance that matches the outputimpedance of said DAC.
 7. The DAC drive circuit of claim 6, said op ampfeedback circuit comprising first and second resistors connected inseries between the amplifier output and the voltage reference node thatcorresponds to an OFF bit output, and a third resistor and a switchconnected in series between the amplifier's inverting input and ajuncture of said first and second resistors, said first and secondresistors each having a resistance value of R, said third resistorhaving a resistance value of R/2, and said switch being permanently ONand matching the switches in the DAC's switching network.
 8. The DACdrive circuit of claim 1, said amplifier comprising an operationalamplifier having its non-inverting input connected to receive the DACoutput and its inverting input connected in a feedback circuit with itsoutput, said feedback circuit having an input impedance that matches theoutput impedance of said DAC.
 9. A digital-to-analog converter (DAC)drive circuit, comprising: high and low reference nodes for supplyinghigh and low reference voltage levels, a DAC that is connected toreceive an input digital signal and to produce a corresponding analogoutput signal with a voltage swing that is limited to the voltage rangebetween said high and low reference voltage levels, divided by a factorD, and an operational amplifier supplied with power from said high andlow voltage reference nodes, said amplifier having a permissible inputsignal range that is less than the difference between said high and lowreference voltages, said amplifier being connected to amplify its inputby said factor D, and thereby produce an amplified output that can swingsubstantially through the full range between said high and low referencevoltage, said amplifier having its non-inverting input connected toreceive the DAC output and its inverting input connected in a feedbackcircuit with its output, said feedback circuit having an input impedancethat matches the output impedance of said DAC.
 10. The DAC drive circuitof claim 9, said divider comprising an attenuation network that isimpedance matched to the DAC.
 11. The DAC drive circuit of claim 10,wherein said attenuation network is implemented as m dummy bits in themost significant bit positions of said DAC, said DAC being connected toreceive an n-bit input digital signal and, including said dummy bits,having n+m bits, said dummy bits being held OFF.
 12. A digital-to-analogconverter (DAC) drive circuit, comprising: a DAC that is connected toreceive an input digital signal and to produce a corresponding analogoutput signal with a predetermined swing range, an operational amplifierthat is connected to receive an analog input from said DAC and toprovide a drive output, said amplifier having a permissible input signalrange that is less than the DAC's analog output signal swing range, anda divider that is connected to reduce the DAC's analog output swing to arange that is within the amplifier's permissible input signal range,said amplifier receiving its input from said DAC through said dividerand providing its output with a greater than unity amplification, saidamplifier having its non-inverting input connected to receive the DACoutput and its inverting input connected in a feedback circuit with itsoutput, said feedback circuit having an input impedance that matches theoutput impedance of said DAC.
 13. The DAC drive circuit of claim 12,wherein said amplifier amplifies its input so that its output has arange that extends over substantially the full swing range of the DAC'sanalog output signal.
 14. The DAC drive circuit of claim 13, whereinsaid amplifier amplifies its input signal by a factor that is theinverse of the DAC output swing reduction provided by said divider. 15.The DAC drive circuit of claim 12, wherein said divider reduces theDAC's analog output swing by half, and said amplifier amplifies itsinput signal by two.
 16. The DAC drive circuit of claim 15, said dividercomprising an attenuation circuit network that is impedance matched tothe DAC.
 17. The DAC drive circuit of claim 15 , 16, wherein saidattenuation network is implemented as a dummy bit in the mostsignificant bit position of said DAC, said DAC being connected toreceive an n-bit input digital signal and, including said bit, havingn+l bits, said dummy bit being held OFF.
 18. The DAC drive circuit ofclaim 12, said divider comprising an attenuation network that isimpedance matched to the DAC.
 19. The DAC drive circuit of claim 18,wherein said attenuation network is implemented as m dummy bits in themost significant bit positions of said DAC, said DAC being connected toreceive an n-bit input digital signal and, including said dummy bits,having n+m bits, said dummy bits being held OFF.
 20. A digital-to-analogconverter (DAC) drive circuit, comprising: a pair of voltage referencenodes for supplying different reference voltage levels, a DAC that isconnected to receive an input digital signal, and to be supplied by saidvoltage reference nodes, an amplifier that is connected to receive ananalog input from said DAC and to provide a drive output, said amplifierhaving a permissible input signal range that is less than the full rangebetween said reference voltage levels, and a divider that is connectedto reduce the DAC's analog output swing to a range that is within theamplifier's permissible input signal range, said amplifier receiving itsinput from said DAC through said divider, and providing its output witha greater than unity amplification, said divider comprising anattenuation network that is impedance matched to the DAC, saidattenuation network implemented as m dummy bits in the most significantbit positions of said DAC, said DAC being connected to receive an n-bitinput digital signal and, including said dummy bits, having n+m bits,said dummy bits being continually held OFF, said DAC comprising an R-2Rladder and an associated switching network for connecting each of its nleast significant bits (LSBs) respectively to one or the other of saidvoltage reference nodes, said switching network including respectivepairs of switches connected in circuit with an 2R resistor of each ofsaid n LSBs, with one switch of each pair connecting its respective 2Rresistor to one of said voltage reference nodes and the other switch ofeach pair connecting its respective 2R resistor to the other of saidvoltage reference nodes, and a control network that turns one switch ofeach pair ON and the other switch of each pair OFF in accordance withsaid input digital signal, said dummy bits each including a singleswitch connecting an associated 2R dummy bit resistor to one of saidvoltage reference nodes that corresponds to an OFF bit output, with saidsingle switch held ON for all digital inputs, said amplifier comprisingan operational amplifier having its non-inverting input connected toreceive the DAC output and its inverting input connected in a feedbackcircuit with its output, said feedback circuit having an input impedancethat matches the output impedance of said DAC.
 21. The DAC drive circuitof claim 20, said op amp feedback circuit comprising first and secondresistors connected in series between the amplifier output and thevoltage reference node that corresponds to an OFF bit output, and athird resistor and a switch connected in series between the amplifier'sinverting input and a juncture of said first and second resistors, saidfirst and second resistors each having a resistance value of R, saidthird resistor having a resistance value of R/2, and said switch beingpermanently ON and matching the switches in the DAC's switching network.22. A digital-to-analog converter (DAC) drive circuit, comprising: apair of voltage reference nodes for supplying different referencevoltage levels, a DAC that is connected to receive an input digitalsignal, and to be supplied by said voltage reference nodes, an amplifierthat is connected to receive a analog input from said DAC and to providea drive output, said amplifier having a permissible input signal rangethat is less than the full range between said reference voltage levels,and a divider that is connected to reduce the DAC's analog output swingto a range that is within the amplifier's permissible input signalrange, said amplifier receiving its input from said DAC through saiddivider and providing its output with a greater than unityamplification, said amplifier comprising an operational amplifier havingits non-inverting input connected to receive the DAC output and itsinverting input connected in a feedback circuit with its output, saidfeedback circuit having an input impedance that matches the outputimpedance of said DAC.
 23. The DAC drive circuit of claim 22, whereinsaid amplifier amplifies its input so that its output has a range thatextends over substantially the full range between said reference voltagelevels.
 24. The DAC drive circuit of claim 23, wherein said amplifieramplifies its input signal by a factor that is the inverse of the DACoutput swing reduction provided by said divider.
 25. The DAC drivecircuit of claim 22, wherein said divider reduces the DAC's analogoutput swing by half, and said amplifier amplifies its input signal bytwo.
 26. The DAC drive circuit of claim 25, said divider comprising anattenuation network that is impedance matched to the DAC.
 27. Adigital-to-analog converter (DAC) drive circuit, comprising: a pair ofvoltage reference nodes for supplying different reference voltagelevels, a DAC that includes a conversion section connected to receive adigital input signal and convert the digital signal to an analog outputsignal, and an attenuation section, said DAC connected to be supplieddirectly by both of said voltage reference nodes at the full referencevoltage levels, and an amplifier having an input that is connected toreceive the analog output from said DAC and to provide a drive output,said amplifier having a permissible input signal range that is less thanthe full range between said reference voltage levels, and a greater thanunity amplification; said attenuation section connected to said DACconversion section to reduce the DAC's analog output swing to a rangethat is within the amplifier's permissible input signal range.
 28. TheDAC drive circuit of claim 27, wherein said attenuation section includesan attenuation network.
 29. The DAC drive circuit of claim 27, whereinsaid DAC is connected to be supplied directly by both of said voltagereference nodes at the full reference voltage levels.
 30. The DAC drivecircuit of claim 27, wherein said digital input is connected only tosaid conversion section.
 31. The DAC drive circuit of claim 27, saidconversion section comprising multiple DAC bits and said attenuationsection comprising at least one DAC bit, with only the multiple DAC bitsof the conversion section having associated therewith switchescontrolled by said input digital signal.
 32. The DAC drive circuit ofclaim 27, wherein said amplifier amplifies its input so that its outputhas a range that extends over substantially the full range between saidreference voltage levels.
 33. The DAC drive circuit of claim 32, whereinsaid amplifier amplifies its input signal by a factor that is theinverse of a DAC output swing reduction factor.
 34. A digital-to-analogconverter (DAC) drive circuit, comprising: a pair of voltage referencenodes for supplying different reference voltage levels, a DAC that isconnected to receive an input digital signal, and to be supplieddirectly by both of said voltage reference nodes at the full referencevoltage levels, and an amplifier that is connected to receive an analoginput from said DAC and to provide a drive output, said amplifier havinga permissible input signal range that is less than the full rangebetween said reference voltage levels, said DAC including an attenuationportion that reduces the DAC's analog output swing to a range that iswithin the amplifier's permissible input signal range, said amplifierproviding its output with a greater than unity amplification.
 35. TheDAC drive circuit of claim 34, wherein said attenuation portion includesan attenuation network.
 36. The DAC drive circuit of claim 34, whereinsaid attenuation portion is not connected to receive said input digitalsignal.
 37. The DAC drive circuit of claim 34, wherein said amplifieramplifies its input so that its output has a range that extends oversubstantially the full range between said reference voltage levels. 38.A digital-to-analog converter (DAC) drive circuit, comprising: high andlow reference nodes for supplying high and low reference voltage levels,a DAC that is connected to receive the full voltage differential betweensaid reference nodes and an input digital signal, and to produce acorresponding analog output signal with a voltage swing that is limitedto the voltage range between said high and low reference voltage levelsdivided by a factor D, and an operational amplifier supplied with powerfrom said high and low voltage reference nodes, said amplifier having apermissible input signal range that is less than the difference betweensaid high and low reference voltages, said amplifier connected toamplify its input by said factor D, and thereby produce an amplifiedoutput that can swing substantially through th e full range between saidhigh and low reference voltage levels.
 39. The DAC drive circuit ofclaim 38, said DAC comprising a conversion section connected to receivesaid input digital signal and convert it to said analog output signal,and an attenuation section that is connected to said DAC conversionsection to reduce the DAC's analog output swing by said factor D. 40.The DAC drive circuit of claim 39, wherein said attenuation sectionincludes an attenuation network.
 41. The DAC drive circuit of claim 39,wherein said digital input is connected only to said conversion section.42. The DAC drive circuit of claim 39, said conversion sectioncomprising multiple DAC bits and said attenuation section comprising atleast one DAC bit with only the multiple DAC bits of the conversionsection having associated therewith switches controlled by said inputdigital signal.